A New Hardware-security Technique for 5G-AIOT Applications: A Low-cost, Low-power, and High-speed “Dielectric-fuse Breakdown OTP” (dFuse OTP) Fully Integrated on CMOS Platform without Additional Masks

Hybrid CMOS Inverter Comprised of Thin Film Transistors with Hetero-channel for Monolithic 3D-ICs and Ultra-high Resolution Flat-Panel Displays Applications

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Technical Name	Field effect transistors methods of forming same
Project Operator	National Taiwan University
Project Host	-
Summary	The vertical FET structure is integrated with modern FinFET technology. The device architecture can be realized without process modify. The channel length can be scaled down to 10 nm with current of 2400 A/m.
Scientific Breakthrough	-
Industrial Applicability	-
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