The low-temperature defect passivation technology developed by our team can effectively eliminate defects in materials under 250°C, and leads to the improvement of the performance and reliability of devices. The technology has demonstrated the significant performance improvement when applying on GaN-based devices. After the treatment, the conducting current of FET devices is increased with the same operation condition. Moreover, in terms of LED devices, the emission efficiency was enhanced and the forward operating voltage decreased as well.

The invention belongs to the field of low-temperature electrochemical graphitizationis improved by the FFC-Cambridge Process. In comparison to the traditional process, the invention can be at a low temperature of 850oCshorter process time. This strategy can convert carbon blacks into high-value graphite (graphene). The method is simple, low temperature, without adding catalyzer,low-cost. The products have a wide range of applications such as energy storage, catalysis, absorption, separation, processing metal cutter, precision die, aeronautics,astronautics.

A novel 3D-stack LTPO-based display array technology with CBRAM-embedded in a pixel has been successfully developed for the high-resolutionpower-saving near-eye VR/AR displays. Besides, a high-voltage gain CMOS inverter comprised by LTPO architecture is demonstrated acting as a digital driving circuit for the realistic FPD applications.

A Metal-Supported Solid Oxide Fuel Cell (MS-SOFC) unit cell with high electricity power output, stability, thermal-shock, mechanical-shock resistanceanti-redox abilities was successfully produced by a continuous fabrication process. This product can be installed not only in stationary SOFC power system but also in transportation set-up. The core technology of the fabrication process is Atmospheric Plasma Spraying (APS) technique which was employed to produce desired functional oxide lays onto permeable Nickel-base super alloy substrate.

The location of controlled-grain Si island is determined by the pattern of “cooling holes”. The grain size is determined by the distance between “holes” due to lateral grain growth using pulse laser crystallization. This predictability allows the transistorscircuits to stay away from the grain boundaries for monolithic

Materials for power device packaging should endure high temperature, high voltage,high current density to handle various harsh working conditions. We developed Cu NP pasteCu/Sn paste for low temperature bonding technique. No toxic chemicals are present in the synthesis processin the pastes. The pastes can bond Cu substrates at low temperature without applying pressure. The joints possess high melting temperature, high thermal stabilityexcellent mechanical properties.

With rapid evolution of Moores lawsemiconductor technology nodes down to sub-10 nm, advanced devicematerial technologies capable of Å accuracy are highly demanded. Thus we developed atomic layer technologies including atomic layer deposition, atomic layer annealing, atomic layer epitaxy,atomic layer etching, etc. for extreme control of materialsstructures with Å precision.

Electroplated nanotwinned Cu possesses excellent electrical & mechanical properties. It can be applied in three major joints: 1. Low thermal budget/ low resistance Cu bonding for high performance computing chip. We are able to achieve low temperature bondinginstant bonding. Low temperature bonding is performed at 150°C for 1 h to achieve low contact resistance copper bonding. Instant bonding is performed at 300°C for 5 seconds under a pressure of 90MPa achieve low contact resistance. 2. High strength/ High ductility copper lines in 3D-IC packaging We are able to fabricate high strength foils with tensile strength of 800MPa. After annealing at 150°C for 3 hours, the foil retains a tensile strength of 750MPa. 3. Cu foils for lithium ion battery