"We will demonstrate the following three technical achievements of our joint project: 1. Deployment of HarDNet on GPU (power consumption: 200 Watts) 2. Deployment of HarDNet on FPGA (power consumption: several tens of Watts) [winning 2nd place in the FPGA track, LPCVC 2020] 3. Deployment of HarDNet on lightweight edge devices such as Raspberry Pi (power consumption: single-digit, 10 Watts) [winning 3rd place in the DSP track4th place in the CPU track, LPCVC 2020]"

The technology uses cathodic arc deposition combined with electromagnet field controloptical emission spectroscopy (OES) for the deposition of new functional high entropy alloy (HEA) nitride coatings. The HEA nitride coatings possessed such high hardnessexcellent hydrophobicity with low surface energy which are beneficial for high speed dry cutting. Finally, the coatings were deposited on the micro end mills for cutting test of printed circuit board. The HEA ACZN coated tools can possess high wear resistanceoutperform the uncoated tools at least 4 times of tool lives.

Our technology uses GaN (gallium nitride)SiC (silicon carbide) wide band gap semiconductor materials to develop high radiation hardness semiconductor technologies for space applications. GaNSiC-based materials feature with a strong bondingsmall lattice constant. Furthermore, the displacement energy of GaNSiC-based materials is greater than 10 times that of silicon. Therefore, GaNSiC-based device can exhibit a better radiation hardness than the Si-based devices, indicating that GaNSiC-based electronics are promising for the space applications.

"1. Use PE Cluster to make the calculation reconfigurable,can be modularized into 36X PEs, supporting up to 2160PEs 2. It can be configured as an independent IP with high computing throughputlow power consumption. The computing performance can reach 864 GOPS@200MHz when 2160PEs are employed."

This research presents a genetic variant discovery SoC for analyzing Next-generation sequencing data which is embedded with the processorconnected with some peripherals. With hardware-optimized algorithm sBWT, we greatly speed up the process of short reads mapping by k-ordered FM-indexsuffix grouping. After short reads mapping, we utilized de bruijn graph for sequence assembly to rebuild haplotypes,built haplotypes are compared to the reference genome to detect genome variations. The detected variations are written to files for further clinical diagnosisresearch analysis.

"1. Automatically generate Verilog code tools based on the hardware architecture of convolutional neural networks: 4 different hardware architectures (output stationary, weight stationary, Tree architecture, NVDLA) can be generated for the currently more commonly used DNN networks. 2. Visual performance index analysis tool: According to the selected DNN model,the choice of hardware architecture specifications, analyze the performance index."

Low-power deep learning accelerator integrates neural network design / training, model compressionaccelerator design. It uses a small amount of computationmemory footprint to realize high performance on the edge device. The image semantic segmentation technology can reach 80 frames per second (resolution:1024*2048) to meet real-time requirements for autonomous driving.

We proposed a dynamic-key secure DFT structure that can generate the keys dynamicallydefend scan-basedmemory attacks without decreasing the system performancethe testability. Analysis results show that our method can achieve a very high security levelthe security level will not decrease no matter how many times the attacker guesses due to the dynamic characteristic of our method.

We developed a wearable ultrasound monitoring device to monitor the collapse of tongue roots of sleep respiratory patients throughout the night,completed clinical trials in the sleep center. The experimental results show that this device can effectively monitor OSA. The tongue structure changes at the timeintegrates ultrasound information into the commercial PSG system. It is expected