STT-MRAM: scaling down (submicron scale) along with issues of magnetic propertyintegration with semiconductor processing. SOT-MRAM: fundamental understanding on mechanism, integration with STT-MRAMCMOS for readout. VCMA-MRAM: understand the mechanism behind the observable VCMA phenomenon, integration with other RAMs for write/read.

This project developed a CMOS Image Sensor (CIS) for the 2nd generation remote sensing satellite,its main achievement is to improve the ground resolution (also known as the Ground Sampling Distance, GSD) from 2 meters to sub-meter. The 12-cm large size chip of CMOS image sensor is implemented using Back-Side Illumination (BSI) CIS technology with mask stitching technologyutilizing the CMOS Time Delay Integration (CMOS TDI) technology in this design.

A CMOS image sensor is developed for the national space organization (NSPO) 3rd generation high-resolution remote sensing satellite,the main achievement is its capability to satisfy the demanded ground resolution of 0.5 m. This CMOS image sensor with a new time delay integration circuit is implemented using Back-Side Illumination CIS 0.13 μm technology. The anti-radiation capability of the chip is also boosted to extend the lifetime of the chip. Measurement systemdata analysis programs are developed to provide performance parameters of the proposed CMOS image sensor.