With the ubiquity of artificial intelligence, dedicated chips to acceleration its computation is required. “Compute-in-memory” performs matrix vector multiplications using a memory array in an analog manner, enabling large throughput, high power and area efficiency. Memory devices based on ferroelectric material have both small area and good endurance, which makes it a promising candidate technology.

This technology covers semiconductor processes, devices, circuits, system architecture and software aspects. Ferroelectric devices (transistors) are successfully fabricated using Taiwan Semiconductor Research Institute’s HfZrO2 process and our unique device design. For circuits, we developed a novel simulation platform to predict the circuit’s power consumption, speed, and computational accuracy. We actively participate in the AITA alliance, led by ITRI, to set the standard for compute-in-memory, and apply our model to industrial standard architecture and compiler framework.

Conventional Lead-Zirconium-Titanite ferroelectric memory may cause contamination in a semiconductor process, therefore it is difficult to integrate with standard CMOS beyond 130nm. Around 2007, hafnium-zirconium-oxide was discovered as new ferroelectric material. We have successfully fabricated HZO ferroelectric memory transistors at Taiwan Semiconductor Research Institute. Key technologies developed are:
1.A special annealing technique to increase the yield of transistors. Similar approaches have been pursued at NamLab (Germany), UC Berkeley and Notre Dame University (USA).
2.We developed corresponding software for the simulation of in-memory computing applications. Teams with similar software include Georgia Tech, IBM, Sandia National Lab (USA), and National Taiwan University.

1.Semiconductor fabrication companies may use our technology to introduce new materials, and improve the effectiveness of memory products
2.IC Design Houses may use our technology to design their artificial intelligence accelerator products